The present invention relates to a memory device, and more particularly, to a circuit and method for sensing the memory cells of the memory device.
A resistance-based memory device normally comprises an array of memory cells, each of which includes a memory element and a selection element, such as transistor, coupled in series between two electrodes. The selection element functions like a switch to direct current or voltage through the selected memory element coupled thereto. Upon application of an appropriate voltage or current to the selected memory element, the resistance of the memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
FIG. 1 is a schematic circuit diagram of a memory array 20, which comprises a plurality of memory cells 22 with each of the memory cells 22 including a selection transistor 24 coupled to a resistance-based memory element 26; a plurality of parallel word lines 28 with each being coupled to the gates of a respective row of the selection transistors 24 in a first direction; a plurality of parallel bit lines 30 with each being coupled to a respective row of the memory elements 26 in a second direction substantially perpendicular to the first direction; and a plurality of parallel source lines 32 with each being coupled to a respective row of the selection transistors 24 in the first or second direction.
Alternatively, the selection transistor 24 in the memory cell 22 may be replaced by a two-terminal bi-directional selector to simplify the wiring scheme and allow stacking of multiple levels of memory arrays. FIG. 2 is a schematic circuit diagram of a memory array 40 incorporating therein two-terminal selectors as selection elements. The memory array 40 comprises a plurality of memory cells 42 with each of the memory cells 42 including a two-terminal bi-directional selector 44 coupled to a resistance-based memory element 46 in series; a first plurality of parallel conductive lines 48A-C with each being coupled to a respective row of the memory elements 46 in a first direction; and a second plurality of parallel conductive lines 50A-C with each being coupled to a respective row of the two-terminal selectors 44 in a second direction substantially perpendicular to the first direction. Accordingly, the memory cells 42 are located at the cross points between the first and second plurality of conductive lines 48A-C and 50A-C. The first and second plurality of conductive lines 48A-C and 50A-C may be bit lines and word lines, respectively, or vice versa. Multiple layers of the memory array 40 may be stacked to form a monolithic three-dimensional memory device.
The resistance-based memory elements 26 or 46 may be classified into at least one of several known groups based on their resistance switching mechanism. The memory element of Phase Change Random Access Memory (PCRAM) may comprise a phase change chalcogenide compound, which can switch between a resistive phase (amorphous or crystalline) and a conductive crystalline phase. The memory element of Conductive Bridging Random Access Memory (CBRAM) relies on the statistical bridging of metal rich precipitates therein for its switching mechanism. The memory element of CBRAM normally comprises a nominally insulating metal oxide material, which can switch to a lower electrical resistance state as the metal rich precipitates grow and link to form conductive paths upon application of an appropriate voltage. The memory element of Magnetic Random Access Memory (MRAM) typically comprises at least two layers of ferromagnetic materials with an insulating tunnel junction layer interposed therebetween. When a switching current is applied to the memory element of an MRAM device, one of the ferromagnetic layers will switch its magnetization direction with respect to that of the other magnetic layer, thereby changing the electrical resistance of the element.
FIG. 3 shows an exemplary current-voltage (I-V) response plot for a bi-directional two-terminal selector. The I-V response curve 60 shows the magnitude of electric current passing through the two-terminal selector element as the voltage applied thereto varies. Initially, the current slightly increases with the applied voltage from zero to near a threshold voltage, Vth. At or near Vth, the current rapidly increases and exhibits a highly non-linear exponential behavior, indicating a transition of the selector from a nominally insulative or “off” state to a nominally conductive or “on” state. As the selector voltage continues to increase beyond Vth, the current increase becomes gradual until reaching VP, which may be the programming voltage required to drive a switching current through a memory element coupled to the selector. The current response behaves like a step function as the applied voltage increases from zero to VP with the sharp increase occurring at or near Vth, which may be about 60-80% of VP. As will be shown later, during the programming operation, the unselected memory cells coupled to either the selected word line or the selected bit line are subjected to a net applied voltage equivalent to about half the programming voltage. Therefore, the leakage current, Ileak, for the selector in the “off” state is measured at the selector voltage of VP/2. The ratio of Ion, which is the selector current at VP, to Ileak measured at VP/2 is sometimes referred to as “on/off ratio.”
With continuing reference to FIG. 3, as the selector voltage decreases from VP to near a holding voltage, Vhold, which is lower than Vth, the selector current gradually decreases and the selector remains in the conductive state. At or near Vhold, the current rapidly decreases and exhibits a highly non-linear behavior, indicating a transition from the nominally conductive state back to the nominally insulative state. As the voltage continues to decrease beyond Vhold, the current flow slightly decreases until stopping at about 0 V.
The I-V response curve 60 of the selector behaves like a hysteresis loop. The nominally insulating selector turns on or becomes conductive when the selector voltage exceeds Vth. Once in the conductive state, the selector will stay on or remain conductive until the selector voltage dropping below Vhold, which is less than Vth. In a conventional write or programming operation, the selector is first turned on by raising the selector voltage to about Vth. The selector voltage is then further increased to a higher level VP that is sufficient to drive a current Ion for switching the resistance state of the memory element coupled thereto. In a conventional read or sensing operation, the selector is first turned on by raising the selector voltage to about Vth. The selector voltage is then decreased to a level between Vth and Vhold to minimize “read disturbance” while ensuring that the selector is sufficiently conductive to allow a sensing current to pass therethrough for determining the resistance state of the memory element.
The two-terminal selector characterized by the I-V response plot of FIG. 3 is bi-directional as the polarity of the selector voltage may be reversed from zero to V′P as shown. The I-V response curve 60′ corresponding to the opposite polarity may be substantially similar to the curve 60 described above. The two response curves 60 and 60′ for the selector are therefore substantially “symmetric” with respect to the current (vertical) axis at Selector Voltage=0. However, a selector may alternatively have an “asymmetric” profile in which at least one of the parameters, VP, Vth, Vhold, and Ion, is not symmetric.
A bi-directional selector may alternatively have an I-V response shown in FIG. 4. The I-V response plot of FIG. 4 differs from the I-V response plot of FIG. 3 in that after the selector is turned on at Vth, the current remains substantially constant with continuously increasing selector voltage or decreasing selector voltage until reaching Vhold, below which the selector is turned off. The constant current is sometimes referred to as “compliance current” (Icc).
FIG. 5 illustrates a scheme for selecting a memory cell in the memory array 40 of FIG. 2 for sensing or programming by turning on the selector of the cell. Referring now to FIG. 5, the memory cell 42BB is selected by applying a voltage, V, to one of the first conductive lines 48B coupled thereto, while grounding one of the second conductive lines 50B connected to the memory cell 42BB, thereby generating a potential difference of V across the memory cell 42BB. Meanwhile, to minimize current leakage and prevent accidental programming of the unselected memory cells, a voltage of about V/2 is applied to the unselected second conductive lines 50A, 50C-D, and the unselected first conductive lines 48A, 48C, resulting in a potential difference of V/2 across the unselected memory cells 42BA, 42AB, 42CB, 42DB, 42BC that are coupled to either the selected first conductive line 48B or the selected second conductive line 50B. The cell voltage of V is greater than Vth to ensure that the selector of the selected memory cell 42BB becomes conductive, while the cell voltage of V/2 is not high enough for the selectors of the unselected memory cells 42BA, 42BC, 42AB, 42CB, and 42DB to become conductive. The rest of the unselected memory cells 42AA, 42CA, 42DA, 42AC, 42CC, and 42DC that are not connected to the selected first conductive line 48B or the selected second conductive line 50B experience essentially no potential drop thereacross.
In a conventional read or sensing operation for determining the resistance state of the selected memory cell 42BB in the memory array 40, a read current is applied to the selected memory cell 42BB after the selector is turned on and the resulting cell voltage is measured and compared to a reference value. Alternatively, a read voltage may be applied to the selected memory cell 42BB after the selector is turned on and the resulting current is measured and compared to a reference value to determine the resistance state.
Some types of resistance-based memory elements, such as MRAM, have almost unlimited read/write endurance but relatively smaller sensing margin compared with other types of memory elements, such as phase change random access memory (PCRAM) and resistive random access memory (ReRAM). The resistance ratio of high-to-low resistance state of MRAM is about 2-4, compared with 102-105 for PCRAM and ReRAM. Therefore, there is a need for a sensing scheme with increasing sensing margin to accommodate all types of memory elements.